When testing high speed Integrated Circuits (ICs), it is desirable to test them using signals whose frequencies are equal to the specified operating frequencies of the IC. Built-In Self-Test (BIST), which requires supplying on-chip generated patterns to a Circuit Under Test (CUT), is often able to generate signals at the required frequencies using only a master clock signal supplied to the IC at the appropriate frequency. However, generating even one high frequency clock for a high speed IC is difficult if the Automatic Test Equipment (ATE) testing the IC does not have a frequency range high enough. Some manufacturers place crystal oscillator on the ATE interface board to generate the high frequency clock (e.g. 50 to 200 MHz). However, this is not a general solution, especially for application-specific ICs (ASICs) in which logic circuits are designed using a hardware description language (HDL), synthesized into logic gates, and automatically arranged in a layout to form an ASIC's physical design. The crystal oscillator must be changed for each ASIC type tested, and several crystal oscillators may be required for a single ASIC.
For many years, designers have incorporated ring oscillators into IC designs to generate periodic signals. A ring oscillator of a basic design comprises an odd-number of inverting delay elements 12 connected in series to form a ring 10, as shown in FIG. 1. By using a control signal ENABLE 13, a reset logic gate 11 allows the oscillation to be stopped in a pre-determined state to have power, and allows controlled start-up of oscillation. The fewer the number of logic gates 11, 12, the higher the oscillation frequency of the output clock signal 14, but three is the minimum. The output of a single inverting gate whose output is connected to its input will simply settle to a stable DC voltage mid-way between logic 1 and logic 0.
When the delay elements 12 in a ring oscillator are simple loci inverters as shown in FIG. 1, the oscillation frequency is dependent on temperature, power supply voltage, and variations in the IC manufacturing process. For this reason, digital ring oscillators are generally not used when accurate frequencies are needed. Delay elements comprising analog circuits can be less sensitive, but are generally not suitable for automated design and layout because the exact layout is important for correct operation, and the deign must be re-optimized for each new IC manufacturing process.
Digitally programmable ring oscillators are one solution to the frequency inaccuracy of digital oscillators. In a digitally programmable ring oscillator, by digitally increasing or decreasing the number of delay elements in the ring, the oscillation frequency can be changed. Decreases in the number of delay elements are always achieved by bypassing some delay elements in one way or another, e.g., a programmable ring oscillator disclosed in U.S. Pat. No. 4,517,532 issued to Neidorff in May 1985. In this oscillator, the resolution of frequency changes is limited by the delay of each delay element used because an even number of inverters must always be added or subtracted from the ring to maintain oscillation. Also, each time the number of inverters in the ring is changed, a transient pulse or "glitch" can be generated at the output.
In a paper entitled, "Integrated Pin Electronics for VLSI Functional Testers" (Gasbarrow & Horowitz, April 1989, IEEE Journal of Solid-State Circuits), the authors show a circuit technique, as shown in circuit 20 of FIG. 2, to create a delay line with delay increments less than that of one logic gate. The circuit 20 is used to delay the rising edges of a series of pulses. The designers exploit "the difference in path delay through pairs of carefully sized inverters." The circuit 20 uses a conventional tapped delay line 24 and multiplexer 23 for the larger delay steps, and parallel inverters 21 and 22, and 25-27 for the smaller delay steps. The transistor sizes of the inverts 21-22, 25-27 are shown next to each inverter in FIG. 2.
Certain characteristics of the design by Gasbarrow & Horowitz can be improved. The authors do not explain how to construct their circuit using only logic gates of a single size. Also, the load capacitance presented by one or two logic gate inputs in present IC technologies is usually too small to cause a significant delay change when the drive of a gate is doubled. Their design, as described, is not suitable for automated design.
U.S. Pat. No. 5,013,944 issued to Fischer et al in May 1991 describes a "Programmable Delay Line Utilizing Measured Actual Delays to Provide a Highly Accurate Delay". The delay line is schematically depicted in the circuit 30 of FIG. 3. The delay of a series of delay stages 35, 36, 41 is measured by connecting them in a ring oscillator and the delay paths (e.g., path 33) are selectively bypassed with alternate delay paths (e.g., path 34) as needed until the oscillation frequency, and hence delay, is sufficiently close to a reference frequency. The difference in delay of each pair of paths (e.g., path 33 and path 34) is designed to be an approximate value, specifically, the delay of one or more non-inverting logic gates. The ratio of the delay difference of each pair (e.g., 35) to the next pair (e.g., 36) in the delay line is approximately a factor of two, thus achieving a binary-weighted programmable delay line 30. For smaller delay increments, one delay path 42 contains a first logic gate 37, and the other path 43 in the pair contains a second logic gate 38 that has additional logic gates 39 connected in parallel at its output, to increase its delay relative to the first logic gate 37 by less than one logic gate's delay.
Certain characteristics of the design by Fischer et al can cause problems. When the capacitive wire load on the gates in each of two paths is not well matched, the delay through the path 33 with fewer logic gates can inadvertently become longer than the path 34 with more logic gates in series. This prevents a binary search algorithm from working correctly. Also, because the two paths 42 and 43 are connected to different inputs of logic gate 40, the two inputs can have different switching point voltages which can cause the delay of the shorter path 42 to appear longer than the intended longer path 43. This effect is exacerbated when additional load capacitance is added to the output of a logic gate. These various effects make the design approach unsuitable for automatic layout. Lastly, for the larger delay changes, glitches can be introduced when switch settings are changed.
If accuracy is to be maintained while a ring oscillator's output is clocking other circuitry, the frequency may need to be changed when it varies significantly from its intended value due to changes in the supply voltage or temperature. Changes in the frequency of a programmable ring oscillator need to be `glitcheless` in such circumstances, otherwise a pulse or `glitch` can be generated which is shorter than the minimum that the clocked circuitry can tolerate, causing incorrect operation. U.S. Pat. No. 5,471,176 issued to Henson et al in November 1995 describes a Glitchless Frequency-Adjustable Ring Oscillator, an embodiment of which is schematically shown in the circuit 50 of FIG. 4. The circuit 50 seeks to avoid introducing glitches in the output signal 55 when delay stages of a tapped delay line 53 are bypassed by synchronizing the switch activation instant of a synchronized switch 54 to the signal in the oscillation ring 50. It also requires only incrementing or decrementing the binary control code and use of a binary-to-Gray code converter 51, so that only one switch is activated/deactivated for each frequency change. The frequency updates are made precisely when the delay line 53 taps immediately adjacent to the presently accessed tap are known to have the same logic value which is achieved by including delay gates 52. The smallest delay changes are limited to the delay of a single logic gate. When this delay gets very small, this approach is sensitive to wire capacitance and to differences in logic gate switching point voltages, and is therefore not suitable for automatic layout on an IC.
A variation 70 of the tapped delay line is shown in a ring oscillator 60 in FIG. 5 is similar to that disclosed in U.S. Pat. No. 5,815,043 issued to Chow et al in September 1998 entitled "Frequency Controlled Ring Oscillator Having By Passable States". The delay line 70 uses the same principle as that described by Fischer et al. The output frequency 65 of the ring oscillator 60 is compared with a reference frequency 66 in control unit 64, and the delay stages 71, 72 and 73 are selectively bypassed with switches 61, 62 and 63 as needed until the oscillation frequency is sufficiently close to the reference frequency. The bypass switches 61, 62 and 63 are connected across every delay stage 71, 72 or 73, instead of using the tapped delay line 53 of FIG. 4 in which a multiplexer 56 bypasses multiple delay stages. Each delay stage 71, 72 or 73 of the delay line 70 is designed to implement exactly twice the delay of the next smaller delay stage, though the patent recognizes that the factor two will be only approximated in the manufactured circuit. The ring oscillator 60 of FIG. 5 can generate glitches if the bypass switch for a delay stage is changed when the input and output of the delay sage have different logic values. The bypass switches described therein apparently `short-circuit` the input and output of each delay stage as a means of bypassing the delay stage. Bypass means could be used which do not employ a short-circuit, for example a multiplexer, though this is not mentioned in the patent. However, in this case, when the delay of a delay stage is less than a logic gate delay, differences in wire capacitance or multiplexer input switching point voltages can cause the problems previously described for FIG. 3. To achieve a wide range of frequencies, e.g. with 6 binary-weighted control bits, the maximum frequency is limited to that corresponding to the delay through 6 stages because the number of by-passable delay stages is equal to the number of bits. If fewer stages are used to attain a high maximum frequency, then the frequency range is proportionally reduced.
To allow automated creation of circuitry to perform built-in testing, it is desirable to automatically synthesize an on-chip oscillator whose frequency can be periodically or intermittently measured and adjusted to achieve high accuracy (e.g. &lt;2%) at any frequency up to the maximum typically used in a particular technology. In the prior art described above, high accuracy was not an objective for the chosen applications. However, high accuracy is very important in production testing. It is therefore desirable to provide an accurate programmable ring oscillator whose design can be automatically synthesized from an HDL description to produce a digital circuit suitable for automatic layout in any IC manufacturing technology, with a conventional library of logic gates.